1. Field of the Invention
The present invention relates to a capacitor structure, and more particularly, to a capacitor structure with greater flexibility of layout design.
2. Description of the Prior Art
A capacitor structure includes two parallel electrode plates and an insulator disposed between the electrode plates. U.S. Pat. No. 5,583,359 discloses a conventional flat plate capacitor structures. Please refer to FIG. 1, which shows an oblique view of the conductive electrodes of a conventional flat plate capacitor structure 10, with the dielectric layers omitted for clarity. As shown in FIG. 1, the conventional flat plate capacitor structure 10 comprises a first level capacitor pattern (bottom electrode) 16, a second level capacitor pattern 19, a third level capacitor pattern 24, and a fourth level capacitor pattern 28. The first capacitor level capacitor pattern 16 has a main portion 56, a protecting ring 57, and a connecting bar 75; the second capacitor level capacitor pattern 19 has a main portion 60, a protecting ring 61, and a connecting bar 75; the third capacitor level capacitor pattern 24 has a main portion 64, a protecting ring 65, and a connecting bar 75; and the fourth capacitor level capacitor pattern 28 has a main portion 68, a protecting ring 69, and a connecting bar 75.
Sets of conductive vias 70, 72 and 74 are defined between adjacent level capacitor patterns, with separate connecting bars 75 of each conductive layer interconnecting the vias, which connect alternate level capacitor patterns to the same voltage. Accordingly, the main portion 56, the main portion 64, the protecting ring 57, the protecting ring 65, the connecting bar 75 of the second capacitor level capacitor pattern 19, and the interlayer conductive vias 70, 74 form a first electrode of the conventional flat plate capacitor structure 10, while the main portion 60, the main portion 68, the protecting ring 61, the protecting ring 69, the connecting bar 75 of the third capacitor level capacitor pattern 24, and the interlayer conductive vias 72 form a second electrode of the conventional flat plate capacitor structure 10.
Conventional flat plate capacitor structure 10 is configured as a stacked capacitor equivalent to a plurality of capacitors in parallel. The capacitance is determined by the overlap of the main portions of the level capacitor patterns. However, the capacitor dielectric layer, and these main portions of the conventional flat plate capacitor structures 10 is stacked up horizontally, and the overlapping region takes a large layout area for a needed capacitance. Therefore, the layout of the conventional flat plate capacitor structure 10 reduces the density of integration.